Low Latency Applications Benefit from Intel 5500 Chips

Developers of low latency trading and market data applications are likely to benefit from new Intel Xeon 5500 Series microprocessors introduced today. Based on Intel's new Nehalem architecture, the chips are expected to offer much improved performance and less power consumption compared to current chips, especially in the areas of multi-threading, memory access, interconnect technology for co-processors and XML processing.

"The London Stock Exchange recognises the importance of both low latency and latency consistency in the operation of efficient markets. We make extensive ongoing use of the Intel fasterLAB in order to evolve our core business applications and to test the effect of processor-level innovation. We have been able to see the immediate impact of the move to 45nm and scaling to the multi-core Intel Xeon processor 5500 series and beyond. The fasterLAB – being equipped with advanced testing facilities and Intel engineering expertise – is a significant asset to our ongoing software development programs," said LSE CTO Robin Paine, in an Intel statement.

Today's announcement included a dozen dual- and quad-core Xeon chips (codenamed Gainstown), based on a 45nm manufacturing process. Processor speeds range from 1.86 GHz to 3.2 GHz, with power consumption from 80W up to 130W. Chips also vary by quantity of Level 3 cache and speed of the interconnect bus. Chips with six and eight cores are also in the pipeline. Specific performance enhancements found in Nehalem include:

* Multi-threading. Each core will be able to execute two instruction threads simultaneously.
* Turbo Mode. Allows one or more cores to run at a higher frequency, on demand, to deliver more power.
* Integrated memory controller. Eliminating the front-side bus (FSB), found in previous chips, Nehalem reduces memory latency and can now take advantage of faster DDR3 memory.
* QuickPath Interconnect (QPI) technology, providing faster communication with other processors and system components.
* Additional instructions for string processing, which will boost performance of XML processing.
* Support for up to 144 GB of RAM, for data-intensive applications.

While the Nehalem architecture will benefit single-threaded applications (market data feed handlers are an example), the biggest impact will be on applications that can take advantage of multi-threading, such as complex algorithmic trading, derivatives pricing and risk management, and also middleware offerings including GigaSpaces Technologies' XAP.

The onus is now on software developers to ensure that their products can take advantage of parallelism and multi-threading, and so leverage the full potential of the new chips.